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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">PMDEVID, Performance Monitors Device ID register</h1><p>The PMDEVID characteristics are:</p><h2>Purpose</h2>
        <p>Provides information about features of the Performance Monitors implementation.</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_PMUv3_EXT32 is implemented. Otherwise, direct accesses to PMDEVID are <span class="arm-defined-word">RES0</span>.</p>
        <p>If <span class="xref">FEAT_DoPD</span> is implemented, this register is in the Core power domain.</p>

      
        <p>If <span class="xref">FEAT_DoPD</span> is not implemented, this register is in the Debug power domain.</p>

      
        <p>This register is required from Armv8.2 and in any implementation that includes <span class="xref">FEAT_PCSRv8p2</span>. Otherwise, its location is <span class="arm-defined-word">RES0</span>.</p>

      
        <div class="note"><span class="note-header">Note</span><p>Before Armv8.2, the PC Sample-based Profiling Extension can be implemented in the external debug register space, as indicated by the value of <a href="ext-eddevid.html">EDDEVID</a>.PCSample.</p></div>
      <h2>Attributes</h2>
        <p>PMDEVID is a 32-bit register.</p>
      <p>This  register is part of the <a href="pmu.html">PMU</a> block.</p><h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="24"><a href="#fieldset_0-31_8">RES0</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">PMSS</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">PCSample</a></td></tr></tbody></table><h4 id="fieldset_0-31_8">Bits [31:8]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-7_4">PMSS, bits [7:4]</h4><div class="field">
      <p>PMU Snapshot extension. Defined values are:</p>
    <table class="valuetable"><tr><th>PMSS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>PMU snapshot extension not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>PMU snapshot extension implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_PMUv3_SS</span> implements the functionality identified by the value <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-3_0">PCSample, bits [3:0]</h4><div class="field">
      <p>Indicates the level of PC Sample-based Profiling support using Performance Monitors registers.</p>
    <table class="valuetable"><tr><th>PCSample</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>PC Sample-based Profiling Extension is not implemented in the Performance Monitors register space.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>PC Sample-based Profiling Extension is implemented in the Performance Monitors register space.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>As <span class="binarynumber">0b0001</span>, and adds support for PMU.PMPCSCTL.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_PCSRv8p2</span> implements the functionality identified by the value <span class="binarynumber">0b0001</span>.</p>
<p><span class="xref">FEAT_PCSRv8p9</span> implements the functionality identified by the value <span class="binarynumber">0b0010</span>.</p>
<p>If <span class="xref">FEAT_PCSRv8p2</span> is not implemented, then the only permitted value is <span class="binarynumber">0b0000</span>.</p>
<p>From Armv8.2, when <span class="xref">FEAT_PCSRv8p2</span> is implemented, the value <span class="binarynumber">0b0000</span> is not permitted.</p>
<p>From Armv8.9, when <span class="xref">FEAT_PCSRv8p9</span> is implemented, the value <span class="binarynumber">0b0001</span> is not permitted.</p></div><div class="access_mechanisms"><h2>Accessing PMDEVID</h2><p>Accesses to this register use the following encodings:</p><h4 class="assembler">Accessible at offset 0xFC8 from PMU</h4><ul><li>When FEAT_DoPD is implemented and !IsCorePowered(), accesses to this register generate an error response.
          </li><li>Otherwise, accesses to this register are <span class="access_level">RO</span>.
          </li></ul><table class="access_instructions"><tr/><tr/></table></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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